The invention relates to a semiconductor device packaging structure, and particularly to a semiconductor device packaging structure which can minimize wiring length between semiconductor packages to realize high speed operation of electronic equipment and, at the same time, can realize a reduction in size and a reduction in thickness of electronic equipment.
In recent years, high speed processing of an enormous amount of information has become required of digital equipment ranging from personal computers used in the Internet and the like to large-sized computers used in technological calculations on a global scale, and there is an ever-increasing demand for an increase in processing speed of the digital equipment. One conventional method for increasing the processing speed is to minimize a signal wiring distance between mounted LSI chips to realize high density packaging which increases propagation speed of signals. Further, there is a trend toward a rapid increase in operation frequency of microprocessors (hereinafter referred to as xe2x80x9cCPUxe2x80x9d), which is the nucleus of digital equipment, and, for example, digital equipment of which the frequency of CPU reaches 1.5 GHz has been reported. An increase in operation frequency of CPU and, at the same time, the use of an enormous number of semiconductor devices have led to a rapid increase in heat generation. For example, in the case of CPU having an operation frequency of 1.5 GHz, the maximum power consumption amounts to about 70 W, and this heat generation is causative of the hinder of an increase in processing speed. The following semiconductor device has hitherto been proposed as a solution to the above problem of heat generation.
FIG. 1 shows the construction of a conventional semiconductor device packaging structure.
This semiconductor device packaging structure is presently adopted in various types of electronic equipment such as computers and switching systems.
A chip bump 2 provided on one side of a flip chip-type LSI chip 1 is connected to the surface of an electrode on the top surface of an interposer 3. The interposer 3 has on its under surface a BGA (ball grid array) bump 4. This BGA bump 4 is connected to a printed wiring board 6 in its pad. A gap between the LSI chip 1 and the interposer 3 is filled with an underfill resin 5 to prevent a thermal expansion coefficient mismatch between the LSI chip 1 and the interposer 3. These portions are called a semiconductor package and are connected to the printed wiring board 6 through the BGA bump 4. Signal wirings 7 are provided so as to form a multilayer structure within the printed wiring board 6, and, in addition, throughholes 50 are provided for connecting the upper wiring layer to the lower wiring layer.
Since the LSI chip 1 generates a significant level of heat during operation, a heat radiator 70 is mounted on the heat radiating surface of the LSI chip 1. When the adhesion between the heat radiator 70 and the LSI chip 1 in its heat radiating surface is poor, the heat radiation is unsatisfactory. When the heat radiation is unsatisfactory, the LSI chip 1 cannot exhibit the original performance and this affects the operation at a high speed and reliability. Accordingly, a method is adopted wherein a heat conductive adhesive 31 is coated on the backside (top surface in the drawing) of the LSI chip 1 to improve heat conduction between the LSI chip 1 in its heat radiating surface and the heat radiator 70, whereby the LSI chip 1 is controlled at a tolerance upper limit temperature or below. The heat radiator 70 comprises a plurality of heat radiating fins 71 which are provided upright at predetermined intervals. This heat radiating fins 71 are forcibly air cooled by blowing the wind produced by a cooling fan (not shown) against the heat radiating fins 71.
xe2x80x9cNEC Giho,xe2x80x9d Vol. 39, No. 1 (1986), pp 36-41 discloses a cooling technique for supercomputers. According to this technique, a plurality of LSIs are two-dimensionally provided on a ceramic substrate, and a columnar heat radiating stud is provided on each LSI. These heat radiating studs are interposed in heat-conductive blocks, and a cooling water passage is provided on the surface of the heat-conductive blocks to perform cooling. According to this cooling technique, a quantity of generated heat of 40 W per LSI can be tolerated, that is, some effect can be attained.
Further, Japanese Patent Laid-Open Nos. 150714/2000, 150715/2000, and 260901/2000 propose semiconductor plastic packages for high density packaging of multiterminal semiconductor plastic packages of which the power consumption is relatively large, such as microprocessors and ASICs (application specific integrated circuits). In these semiconductor plastic packages, the following means is provided to cope with an improvement in function of LSI chips and with an increase in the quantity of generation of heat involved in increased density of packaging: means for disposing, at the center of an interposer in its thicknesswise direction, a metallic plate having substantially the same size as an interposer; means for fixing an LSI chip onto one side of the interposer with the aid of a heat-conductive adhesive; means for insulating the metallic plate from a circuit provided on the surface through a heat-curable resin composition; means for connecting the circuit conductor provided on the interposer to the LSI chip by wire bonding; means for connecting, through a throughhole conductor insulated by a metallic plate and a resin composition, a signal propagation circuit conductor on a printed wiring board to a circuit conductor or a connection conductor pad provided on the printed wiring board in its side remote from the signal propagation circuit conductor; means for sealing the semiconductor chip, the wire, and the bonding pad with a resin; and the like. In these publications, the material for the metallic plate for heat radiation is not particularly limited. However, materials, which have a high modulus of elasticity and a high coefficient of thermal conductivity and a thickness of 30 to 500 xcexcm, are described to be suitable, and pure copper, oxygen free copper and the like are specifically disclosed.
According to the conventional semiconductor packaging structures, however, in the case of the semiconductor device shown in FIG. 1, the volume occupied by the heat radiator 70 is large. Therefore, the spacing between adjacently mounted LSI chips is long. This necessitates the provision of long signal wiring, which causes attenuation or delay of transmitted signals, and thus cannot cope with a demand for an increase in processing speed in the future. Further, the fact that the occupied volume of the heat radiator 70 is large, means that the above device cannot meet the demand for a reduction in size and a reduction in thickness in advanced electronic equipment.
Further, in the technique described in xe2x80x9cNEC Giho,xe2x80x9d Vol. 39, since the size of the water cooling mechanism is large, the packaging volume cannot be reduced. Therefore, the technique described in xe2x80x9cNEC Giho,xe2x80x9d Vol. 39 also involves the above problem. Further, according to Japanese Patent Laid-Open Nos. 150714/2000, 150715/2000, and 260901/2000, in recent years, many LSI chips, of which the number of terminals exceeds 1000 pins, appear, and an improvement in function would lead to a demand for a further increased number of pins in the future. In the case of the structure wherein the metallic plate is embedded in the whole area within the interposer, this is considered to pose a problem associated with housing of signal wiring and an increase in size of package.
Accordingly, it is an object of the invention to provide a semiconductor device packaging structure which can reduce the mounting volume of a heat sink while providing satisfactory cooling capacity and, at the same time, can minimize the length of signal wiring between LSI chips.
According to the first feature of the invention, a semiconductor device packaging structure comprises: a printed wiring board having mautilayered wirings; and a semiconductor chip mounted at a predetermined position of the printed wiring board,
wherein the printed wiring board is provided with a heat sink at a site remote from the semiconductor chip, and wherein a plurality of metallic columns, which contact the heat sink and a metallic portion on the semiconductor chip side to perform heat link, are built in the printed wiring board.
According to this structure, packaging of a heat sink within a printed wiring board can reduce the space of the heat sink, which occupies the semiconductor device, and, in addition, can reduce spacing between adjacent semiconductor chips. Further, in this case, heat is conveyed from the semiconductor chip to the heat sink through a plurality of metallic columns provided within the printed wiring board. The metallic columns are a minute object and thus have substantially no effect on drawing of wirings or the number of wirings provided within the printed wiring board. Therefore, unlike the conventional construction wherein, due to the mounting of a large heat sink, mutual spacing between semiconductor chips on the printed wiring board is large resulting in large signal wiring length, according to the invention, the signal wiring length between semiconductor chips can be reduced and, thus, attenuation or delay time in the signal transmission can be reduced.
According to the second feature of the invention, a semiconductor device packaging structure comprises: a printed wiring board having mautilayered wirings; and a semiconductor chip mounted at a predetermined position of the printed wiring board,
wherein the printed wiring board is provided with a heat sink at a site remote from the semiconductor chip and has a concave portion for exposing the heat sink, and wherein the semiconductor chip is mounted within the concave portion in such a state that the heat radiating surface of the semiconductor chip is in close contact with the heat sink.
According to this structure, a heat sink is provided within a printed wiring board. This can reduce the space of the heat sink, which occupies the semiconductor device, and, in addition, can reduce the space between adjacent semiconductor chips. Further, a concave portion (an opening portion) is provided in the printed wiring board so as to face the heat sink, and the semiconductor chip can be directly mounted on the heat sink. Therefore, unlike the conventional construction wherein, due to the mounting of a large heat sink, mutual spacing between semiconductor chips on the printed wiring board is large resulting in large signal wiring length, according to the invention, the signal wiring length between semiconductor chips can be reduced and, thus, attenuation or delay time in the signal transmission can be reduced.
According to the third feature of the invention, a semiconductor device packaging structure comprising: a printed wiring board having mautilayered wirings; and a semiconductor chip mounted at a predetermined position of the printed wiring board, wherein
a heat sink having in its interior at least one passage for passing a cooling medium therethrough is mounted on the heat radiating surface of the semiconductor chip.
According to this structure, the heat sink permits a cooling medium to be passed therethrough to enhance the heat change efficiency. This can realize a reduction in size. This heat sink is mounted directly on the surface of the semiconductor chip. Therefore, unlike the conventional construction wherein, due to the mounting of a large heat sink, mutual spacing between semiconductor chips on the printed wiring board is large resulting in large signal wiring length, according to the invention, the signal wiring length between semiconductor chips can be reduced and, thus, attenuation or delay time in the signal transmission can be reduced.